Access Latency Reduction in Contemporary DRAM Memories

Performances of DRAM memories are characterized by memory latency and bandwidth. Contemporary DRAM memories more successfully satisfy demands for higher bandwidth than lower latency. In this paper solutions, which may reduce latency of these memories, are investigated. These solutions are two new controller policies called ’Write-miss Only Close-Page’ and ’Write-miss Only Close-Page-Open previous Page’ as well as several address remapping schemes. ’Write-miss Only Close-Page’ policy is basically a combination of the policies ’Open-Page’ and ’ClosePage-Autoprecharge’. For all DRAM reads ’Open-Page’ policy is used. Also for all DRAM writes that cause row-buffer hits ’Open-Page’ policy is used. For all DRAM writes that cause row-buffer misses ’ClosePage-Autoprecharge’ policy is used. ’Write-miss Only Close-Page-Open previous Page’ policy is the same as ’Writemiss Only Close-Page’, except that after the precharge the previously open row is opened again. Simulations show improvements in using these combined policies. Permutation-based Page Interleaving scheme is known as an effective address remapping scheme for reducing row-buffer conflicts, which are consequence of conflict cache memory misses. This scheme is based on using xor circuits for changing bank indices of data blocks that fit into the same cache memory line set. We improve this scheme by proposing five similar schemes, with slightly better effectiveness. Three of the proposed schemes have approximately the same performances, but do not use xor circuits at all. Two of the proposed schemes use xor circuits but have slightly better performances.